| 摘要 |
PROBLEM TO BE SOLVED: To provide a data processor, for which a timer circuit is not required for refresh control outside a DRAM, concerning the data processor provided with the DRAM. SOLUTION: A refresh timer circuit 4 for self-refresh mode inside a DRAM 1 periodically generates a time-up signal 6 for performing refresh operation for holding cell data. This time-up signal 6 is generated at all the time in spite of the refresh mode and outputted to an outside of the DRAM 1. This time-up signal 6 is transferred to a DRAM control circuit 5 inside a logic LSI 3. In the DRAM control circuit 5, all access requests from plural control parts inside the logic LSI 3 are waited according to this time-up signal 6 and a control signal 7 is outputted to the DRAM 1 at timing required for the refresh operation.
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