| 摘要 |
Methods and devices to reduce processor-to-system memory access latency through the use of a memory buffer (202) for the storage of cache lines flushed (cast out) from conventional level-1 (L1) and/or level-2 (L2) processor caches are described. The memory buffer (202), referred to as a cast-out cache, may be incorporated within a system controller (200) and/or memory controller device (204).
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