| 摘要 |
Floating-point processors (200) capable of performing multiply-add (Madd) operations and incorporating improved intermediate result handling capabilities. The floating-point processor (200) includes a multiplier unit (210, 212) coupled to an adder unit (236, 262). In a specific operating mode, the intermediate result from the multiplier unit (210, 212) is processed (i.e., rounded but not normalized or denormalized) into representations that are more accurate and easily managed in the adder unit (236, 262). By processing the intermediate result in such manner, accuracy is improved, circuit complexity is reduced, operating speed may be increased.
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