| 摘要 |
A processor circuit board (102, 201), according to various aspects of the present invention, includes a first interface (212), a second interface (104, 220, 222), a peripheral circuit (120, 328), a logic circuit (112), and a memory (110). The first interface electrically couples a provided microprocessor (108, 208, 210) to the processor circuit board. The microprocessor comprises indicia of membership in a family of microprocessors of various configurations. The second interface electrically couples a provided application circuit board (172, 203) to the processor circuit board. The peripheral circuit is formed on the processor circuit board. The logic circuit comprises a control register (314) operated via the first interface to provide a control signal (CB2) and a decoupling device (316, 322) responsive to the control signal for selectively decoupling the peripheral circuit from the first interface. The memory is coupled to the first interface and includes indicia of a method to be performed by the provided microprocessor for avoiding an interference between the peripheral circuit and the application circuit. The method includes: (a) reading the indicia of membership; and (b) operating the control register in accordance with the indicia of membership to effect decoupling in response to the control signal.
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