Bit reduction using dither,rounding and error feedback,申请号GB20000031771-传众专利搜索

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发明名称	Bit reduction using dither,rounding and error feedback
摘要
申请公布号	GB0031771(D0)	申请公布日期	2001.02.07
申请号	GB20000031771	申请日期	2000.12.29
申请人	LSI LOGIC CORPORATION	发明人
分类号	G06F7/48	主分类号	G06F7/48
代理机构		代理人
主权项
地址

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