DYNAMIC LOGIC CIRCUIT FOR SAVING POWER CONSUMPTION

摘要

PURPOSE: A dynamic logic circuit is provided to be capable of reducing power consumption by dividing logic blocks according to an operating time and selectively supplying a clock signal to a logic block of an operating state. CONSTITUTION: The first clock generating circuit(10) receives a system clock signal and the first control signal and generates the first clock signal and the second control signal. The second clock circuit(20) receives the system clock signal and the second control signal and generates the second clock signal. The first dynamic logic circuit(30) is operated by the first clock signal, and the first latch circuit(40) stores an output of the first dynamic logic circuit depending on the first clock signal. The second dynamic logic circuit(50) is operated by the second clock signal, and the second latch circuit(60) stores an output of the second dynamic logic circuit depending on the second clock signal.