发明名称 DISPOSITIF DE VERROUILLAGE A DOUBLE SYSTEME INFORMATISE
摘要 A computerized dual-system interlocking apparatus offers a fast processing speed, an improved utilization and an easy-to-test characteristic, with a start/stop function provided in data matching between two CPUs. The apparatus comprises a data matching circuit (16) for determining data match between sets of data resulting from identical processes performed by a first CPU(7) and a second CPU(13) on identical input information, and wait circuits (19, 21) for making the first CPU(7) and second CPU(13) wait in standby for the processes during data matching operation, and for releasing the first CPU(7) and second CPU(13) free from the standby state when the data matching circuit (16) determines that the sets of data match, and a reset circuit (5) for issuing reset signals to the first CPU(7) and second CPU(13) when the sets of data fail to match.
申请公布号 FR2751445(B1) 申请公布日期 2001.02.02
申请号 FR19970002233 申请日期 1997.02.25
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 OKAJIMA TOSHIO;MUKAI ATSUSHI
分类号 B61L19/06;B61L1/20;B61L21/06;G05B9/03;G06F11/16;(IPC1-7):G06F15/163;G06F11/20 主分类号 B61L19/06
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