发明名称 Adjustable bandwidth phase locked loop with fast settling time
摘要 An adjustable bandwidth phase-locked loop including a phase-locked loop having a first input node receiving an input signal having a first frequency, a second input node receiving a feedback signal and an output node which has a signal indicative of an error signal characterizing a frequency error between the input signal and the feedback signal. The adjustable bandwidth phase-locked loop includes a voltage controlled oscillator, coupled to the second input node, receiving the error signal and generating the feedback signal where the feedback signal has a frequency which tracks the first frequency. The adjustable bandwidth phase-locked loop includes a variable loop filter, coupled between the phase-locked loop and the voltage controlled oscillator, filtering the error signal. The variable loop filter is configurable to allow for the tracking of the input signal over both of a broad bandwidth and a narrow bandwidth.
申请公布号 AU5478199(A) 申请公布日期 2001.01.31
申请号 AU19990054781 申请日期 1999.08.11
申请人 DENSO INTERNATIONAL AMERICA, INC. 发明人 JAMES B. KIRKPATRICK
分类号 H03L7/093;H03L7/095;H03L7/10;H03L7/107;H03L7/113 主分类号 H03L7/093
代理机构 代理人
主权项
地址