| 摘要 |
PROBLEM TO BE SOLVED: To improve the ESD resistance in a CMOS semiconductor device having an SOI structure by connecting plugs buried in contact holes through a wiring layer to input pads and contacting them onto a substrate. SOLUTION: Input pads 30, a P+ layer 26 and an N+ layer 28 are interconnected through an Al alloy wiring layer 41, the drain electrodes of P-channel MOS transistors 34 and the drain electrodes of N-channel MOS transistors are interconnected through a wiring layer 42, the source electrodes of the P-channel MOS transistors 34 are interconnected with a power voltage Vdd1 through a wiring layer 43, and the source electrodes of the N-channel MOS transistors are interconnected with a ground voltage Vss1 through a wiring layer 44. Thus the electrostatic breakdown strength can be raised because of no dependence on the wiring patterns, compared with the conventional structure, by making ESD noises penetrating through the input pads 30 escape to the substrate side.
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