| 摘要 |
PROBLEM TO BE SOLVED: To facilitate programming by fixing a combination of a processor core and a data memory from the beginning to the end of a pipeline and to suppress an increase in circuit scale by independently controlling processor core and data memory state transition. SOLUTION: A pipeline processor 1 has n (n>=4) data memories 41, 42, 43, 44, and 45 stored with information being an object of pipeline processing, a means which changes the states of (n-2) processor cores 21, 22, and 23 independently, and a means which fixes a combination of the processor cores 21, 22, and 23 and data memories 41, 42, 43, 44, and 45 from the beginning to the end of the pipeline processing.
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