| 摘要 |
<p>Delay cell having a stable delay with a low voltage power supply, and a high power supply rejection ratio. A first (22) and second (32) input receiver on a first (14) and second (16) branch, respectively, receive an input to control a current on each branch. Each branch includes an output node (24, 34) capacitively coupled to a power supply (12). Each branch may include a current source (28, 38) and/or a lower limit clamp (30, 40) coupled between the output node and the power supply. First and second current diverters (44, 46) may also be coupled for diverting current away from the respective input receivers (22, 32). An upper limit clamp may also be coupled for maintaining the output below an upper limit. The clamp inputs (VSWL, VSWU) may be generated relative to the power supply. A tail current source (18) and upper current source (50) may also be respectively coupled.</p> |
