发明名称 NO STALL READ ACCESS FOR HIDING LATENCY
摘要 The memory space (118) accessible by a processor (28) is partitioned such that multiple memory regions map to the same physical memory. Processor accesses in one of the regions (120, 124) are regarded as normal accesses, and are satisfied from the memory or a read buffer (72, 74). If memory access is required, the processor is stalled until the desired data is returned from the memory. Processor accesses to the other region (122, 126) are regarded as requests to prefetch the data from the memory and place it into a read buffer without stalling the processor. The processor continues program execution while the data is being prefetched. At a later point in program execution, the processor requests the data via the first region. The data likely resides in the read buffer, and can therefore be provided to the processor quickly, resulting in improved performance.
申请公布号 WO0106372(A1) 申请公布日期 2001.01.25
申请号 WO2000US19139 申请日期 2000.07.13
申请人 3COM CORPORATION 发明人 PLATKO, JOHN, J.;CHIEFFO, PAUL
分类号 G06F13/42;(IPC1-7):G06F12/08 主分类号 G06F13/42
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