| 摘要 |
A retiming circuit able to constantly perform sampling by a clock at a center portion of input data and performing a correct discrimination of logic "1" and "0" even if there is duty fluctuation of a pulse, provided with delay unit for imparting a variable delay to input data or a clock; a reference clock generating unit for generating a reference clock synchronized with the clock; a first phase difference detection unit for detecting a phase difference between a rising edge of the reference clock and the rising edge of the input data; a second phase difference detection unit for detecting a phase difference between the rising edge of the reference clock and a falling edge of the input data; and an intermediate phase setting unit for calculating the intermediate phase of the input data based on the outputs of the first and second phase difference detection units, the delay being controlled based on the intermediate phase.
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