| 摘要 |
PURPOSE: A device for controlling internal of a password algorithm chip is provided to generate password algorithms of a plurality of channels with one chip by generating a plurality of password key streams without breaking the synchronization of each algorithm. CONSTITUTION: An input register(201) converts parallel data inputted from an external processor into serial data. The input register(201) outputs the data converted. A linear feedback shift register(202) converts the serial data into linear feedback data. In addition, the linear feedback shift register(202) outputs the data converted. An output register(205) converts the serial data outputted from the linear feedback shift register(202). The output register(205) outputs the data converted to the outside. An output latch circuit(206) latches the parallel data outputted from the output register(205). In addition, the output latch circuit(206) provides the data to the outer processor. A control signal generator(207) respectively generates an output signal for controlling the input register(201), the linear feedback shift register(202), the output register(205) and the output latch circuit(206). A key stream/register selection circuit(211) is connected between the linear feedback shift register(202) and the output register(205). In addition, the key stream/register selection circuit(211) outputs data among key stream data and data outputted from a plurality of shift register according to an output signal of the control signal generator(207).
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