| 摘要 |
A memory access system which generates two memory addresses from a single memory access instruction. The instruction identifies an index register r<SB>c</SB> holding at least two packed objects, a base register r<SB>a</SB> and a destination register r<SB>b</SB> The register access circuit 20 addresses the registers r<SB>a</SB> and r<SB>c</SB> and the values V<SB>a</SB> and W0; W1 are returned to the temporary buffers 22 and 24. The addition circuit 26 and 28 add the offsets of W0 and W1 to V<SB>a</SB> to generate two addresses ADDR1 andADDR2. Thus, the contacts of the base register is combined respectively with each of two or more packed objects in an offset register. Data packing is determined by the SIMD protocol and the system is described as being particularly useful in an MPEG environment. |
