| 摘要 |
A process for fabricating a polycide, dual gate structure, for CMOS devices, featuring an undoped polysilicon layer, located between an overlying metal silicide layer, and an underlying dual doped polysilicon layer, has been developed. A first undoped polysilicon layer is converted to the dual doped polysilicon layer, via formation of an N type doped region, in a first portion of the first undoped polysilicon layer, overlying subsequent nMOS devices, in a P well region, followed by the formation of a P type doped region, in a second portion of the first undoped polysilicon layer, overlying subsequent pMOS devices, in an N well region. A second undoped polysilicon layer is deposited on the dual doped polysilicon layer, to provide a low diffusion coefficient buffer layer, to prevent auto-doping of the dual doped polysilicon layer, as a result of direct dopant diffusion into the overlying, high diffusion coefficient, metal silicide layer, followed by redistribution into the underlying dual doped polysilicon layer. The use of the undoped polysilicon, buffer layer, allows the use of high temperature procedures, such as procedures used with self-aligned contact structures, without the risk of the auto-doping phenomena.
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