发明名称 DATA INPUT APPARATUS OF DDR SDRAM(DOUBLE DATA RATE SYNCHRONOUS DRAM)
摘要 PURPOSE: A data input apparatus of a DDR SDRAM(Double Data Rate Synchronous DRAM) is provided which increases an operation speed by performing a write operation without adding an additional control signal. CONSTITUTION: The device performs a write operation without an additional control signal by converting input data into a pulse signal by synchronizing them to an internal clock pulse signal and applying them to a global data bus. The data input apparatus of a DDR SDRAM includes: a data input unit(430) generating a data signal being inputted from the external of a chip as a rising data signal synchronized to a rising edge of a data strobe signal and a falling data signal of the data strobe signal synchronized to a falling edge of the data strobe signal respectively; the first data align unit(440) generating a data align rising signal and a data align falling signal aligned mutually by synchronizing the rising data signal and the falling data signal to the data strobe signal; the second data align unit(450) generating a clock align rising data and a clock align falling data as an aligned pulse signal by synchronizing the data align rising signal and the data align falling signal to an external clock signal; a switching unit(470) converting the clock align rising data and the clock align falling data into the first and the second internal input pulse signal according to the sequence of data inputted from the external in response to a control signal; and a global data bus input unit(490) transferring data to the first and the second global data bus line in response to the first and the second internal input pulse signal.
申请公布号 KR20010004210(A) 申请公布日期 2001.01.15
申请号 KR19990024831 申请日期 1999.06.28
申请人 HYNIX SEMICONDUCTOR INC. 发明人 RYU, JE HUN;YOO, GI HYEONG
分类号 G11C11/406;(IPC1-7):G11C11/406 主分类号 G11C11/406
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