| 摘要 |
PURPOSE: A CMOS output buffer circuit is provided to reduce peak current and to prevent noise and erroneous operation of circuit by separating driving transistors of output terminal and sequentially driving the transistors with a time interval. CONSTITUTION: A CMOS output buffer circuit comprises an input unit(10) for generating a signal for driving an output unit(30) in accordance with an input signal, the output unit for generating an output signal in accordance with the signal output from the input unit, and a control unit(40) for sequentially turning on driving transistors of the output unit with a time interval, by using the output signals of the input unit and the output unit. The input unit includes a NAND gate(NA1) for taking as an input a data signal(saout) and an enable signal(oeb) through an inverter(NOT1), and a NOR gate(NOR1) for taking as an input the enable signal and data signal. The output unit includes a first driving unit(31) for taking as an input and output signal(dp2) of the NAND gate of the input unit, and which has second and third PMOS transistors(P2,P3) connected in parallel; and a second driving unit(32) for taking as an input an output signal(dn2) of the NOR gate of the input unit, and which has second and third NMOS transistors(N2,N3) connected in parallel.
|
