| 摘要 |
PURPOSE: A method for manufacturing a bit line contact is provided to reduce contact resistance, by making a polysilicon layer of a gate electrode contact a polysilicon layer of a bit line. CONSTITUTION: A gate insulating layer, the first and second conductive layers, the first insulating layer and the second insulating layer are sequentially formed on a semiconductor substrate(200) having a main cell region and a core peripheral region. The second insulating layer on the core peripheral region is removed. The first insulating layer, the second and first conductive layers and the gate insulating layer in the main cell region are patterned to form the first gate pattern. The first insulating layer, the second and first conductive layers and the gate insulating layer in the core peripheral region are removed to form the second gate pattern. A sidewall spacer(260) is formed on a side of the first and second gate patterns with the same material as the second insulating layer. An interlayer dielectric is formed on the substrate including the first and second gate patterns. A predetermined part of the interlayer dielectric in the core peripheral region, the remaining first insulating layer and the second conductive layer is eliminated to form a contact hole exposing the first conductive layer. The third conductive layer having the same material as the first conductive layer is formed on the interlayer dielectric. The fourth conductive layer is formed on the third conductive layer. The third and fourth conductive layers are patterned to form a bit line.
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