发明名称 OUTPUT BUFFER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To improve noise reduction without increasing tr/tf time by enhancing the tr/tf time, without decreasing noise reduction in an output buffer circuit of a CMOS configuration. SOLUTION: Midway of the gate input signal of a PMOS transistor(TR) PM1 of a main driver section 22 transiting from H level to L level, an inverter 20 makes NMOS TRs Ng21,..., Ng2X conductive to charge up a gate capacitance of the PMOS TR PM1. Midway of a gate input signal of a PMOS transistor NM1 of the main driver section 22 transiting from L level to H level, an inverter 27 makes PMOS TRs Pg21,..., Pg2X conductive to charge up the gate capacitance of the NMOS TR NM1. Thus, the time constant is reduced and the speed of the tr/tf time can be increased, while keeping noise reduction.
申请公布号 JP2001007695(A) 申请公布日期 2001.01.12
申请号 JP19990172905 申请日期 1999.06.18
申请人 MITSUBISHI ELECTRIC CORP;MITSUBISHI ELECTRIC ENGINEERING CO LTD 发明人 KATADA KEIKO;KINOSHITA HIROSHI;KAWANO TETSUJI;AIHARA TAKAFUMI
分类号 H03K17/16;H03K19/0175;(IPC1-7):H03K19/017 主分类号 H03K17/16
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