BUS MASTER TRANSFER CIRCUIT FOR MPEG TRANSPORT STREAM

摘要

PROBLEM TO BE SOLVED: To relieve a load on a CPU to the utmost by interfacing an interrupt generating section with a conventional bus and controlling extracted data from a payload/section extract section and data after CRC arithmetic operation from a CRC arithmetic section after transferring them to an address location of a predetermined memory through the conventional bus in terms of bus-master transfer. SOLUTION: A CPU sets information to an information storage section 150 via an conventional bus 2 and a bus interface section 160. When input of a TS as an 8-bit width data stream is started, a TS input section 110 searches for a synchronization byte denoting a head of a TS packet and outputs TS data 11 including synchronization byte position information when detecting the synchronization byte. A payload/section extract section 120 conducts its processing according to an output 151 of the information storage section 150. In the case that a PID enable indicates an enable state, a PID and a PID part of the TS data 111 are compared, no packet is processed and no output is given when the both are dissident.