| 摘要 |
PROBLEM TO BE SOLVED: To automatically predict a chip size when completing the preparation of an IC circuit and to make compatible degradation suppression of chip size conditions and shortening of development turn-around time(TAT). SOLUTION: When an IC designer prepares a circuit diagram, respective circuit elements included in this circuit diagram are extracted, each element is converted to a reference integration enable number per unit packaging area of a basic element, a total packaged element number is calculated and the chip size is predicted from the data of layout and reference integration enable number (integration density) stored in a data base 40. Then, this predicted value is compared with a chip size based on an article plan and when it is within an allowable range, IC layout processing is started. When the chip size is not proper, redesign is performed. After layout in IC layout processing, the integration density is calculated from a real chip size and automatically stored in the data base 40. Besides, the real chip size is compared with the chip size in the article plan and when it is within the allowable range, work is completed.
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