| 摘要 |
PROBLEM TO BE SOLVED: To improve designing accuracy when designing clock interconnections for an LSI having multilayered interconnections by correctively designing the clock interconnections in consideration of the multiple layers. SOLUTION: The LSI designing method comprises: a step S1 of inputting data such as layout information and terminal connection information about elements of an LSI having multilayered interconnections; a step S2 of inserting buffers into timing- affecting interconnections; a step S3 of roughly forming multilayered interconnections for signal lines other than the timing-affecting interconnections; a step S4 of roughly forming the timing-affecting interconnections; a step S5 of selecting multilayered interconnections crossing the timing-affecting interconnections; a step S6 of estimating the volume of the multilayered interconnections selected by the step S5 crossing the timing-affecting interconnections; a step S7 of forming isodelay interconnections for the timing-affecting interconnections; a step S8 of completely interconnecting the signal lines other than the timing-affecting interconnections; and a step S9 of outputting interconnection information. The volume of the multilayered interconnections crossing the timingaffecting interconnections is corrected more with less number of layers through which the timing-affecting interconnections cross the multilayered interconnections.
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