Semiconducting memory has redundancy assessment circuit, control circuit that activates redundancy decoder, deactivates normal word decoder if external address corresp. to faulty cell

摘要

The memory has normal and redundant memory cells, normal and redundant word lines, a normal word decoder (60) for selecting and driving one normal word line in coincidence with external address signals provided depending on a first clock signal, a redundancy word decoder (50) for driving a first redundant word line, an address assessment device (30) for determining whether the external address signal corresp. to a faulty normal memory cell and a redundancy control circuit (40) that activates the redundancy decoder and deactivates the normal word decoder in response to as second clock if the external address signal corresp. to the address of a normal faulty memory cell.