| 摘要 |
The invention concerns a network of elementary parallel processors fault-tolerant towards said processors, comprising said elementary processors, additional elementary processors, elements interconnecting said processors and a control unit, and a succession of lines of interconnecting elements alternating with lines of processors, each processor being enclosed by four interconnecting elements, the lines of processors being lines of elementary processors, the last line of processors being a line of additional processors, the network onboard elements being interconnecting elements, wherein the control unit, connected to the processors and the interconnecting elements, sends instructions to the processors, controls the interconnecting elements, and verifies the integrity of said processors.
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