| 摘要 |
The present invention provides a circuit to transfer data from a first clocked domain to a second clocked domain. The circuit includes a first latch clocked by a first clock signal and a second latch clocked by a second clock signal that is faster than the first clock signal. The circuit further includes a clock enabling circuit to receive the second clock signal and the signal indicating that a transition of the first clock has occurred and to provide the second clock signal to the second latch after the transition of the first clock signal. In another embodiment, the present invention provides a circuit to transfer data from a first clock domain to a second clock domain that is asynchronous with respect to the first clock domain. The circuit includes a first latch sequenced by a first clock signal that has a first frequency and the second latch sequenced by a second clock signal that has a second frequency substantially lower than the first frequency. The circuit also includes a clock enabling circuit to receive the first clock signal and the signal indicating occurrence of a triggering edge of a second clock signal. The clock enabling circuit provides the first clock signal to the first latch when the signal indicates occurrence of the triggering edge of the second clock signal.
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