| 摘要 |
An arrangement (200) and a method are disclosed having a capability of bridging between clock domains in a digital switch. The bridging is accomplished by means of a time slot mapping table (370) containing information typically regarding both time and space switching of the time slot data entries between incoming and outgoing bit streams. By incorporating instructions in the time slot mapping table (370) having the purpose of providing an indication of whether of not to actually transfer data to an output port (330), it is possible to obtain the effect of bridging between the different clock domains. In other words, a selection in made based on the information in the mapping table (370) to obtain a selected subset of time slot data entries to be transferred from an input frame buffer (300) to an output bit stream, the feature of selecting a subset and not the entire set of time slots from input bit streams having the effect of lowering the bit rate. |
