METHODS AND APPARATUS FOR ESTABLISHING PORT PRIORITY FUNCTIONS IN A VLIW PROCESSOR

摘要

Port priorities are defined on a 32-bit word, 16-bit half-word, and 8-bit byte basis to control the write enable signals to a compute register file (CRF) (111, 127, 127', 127", 127'"). With a manifold array (ManArray) reconfigurable register file, it is possible to have double-word 64-bit and single word 32-bit data-type instructions mixed with other double-word, single-word, half-word, or byte data-type instructions within the same very long instruction word (VLIW). Write priority conflicts are resolved on a byte, half-word, or word, allowing partial operations to complete that provide a useful function. For example, a load half-word to the half-word H0 portion of a 32-bit register R0 (402) and R11 (404) will complete its operation on the non-conflicting half-word portions of the 64-bit register R0 and R1. The present approach to assigning port priorities improves the performance of the ManArray indirect VLIW processor (100).