发明名称 COMPREHENSIVE REDUNDANT LOAD ELIMINATION FOR ARCHITECTURES SUPPORTING CONTROL AND DATA SPECULATION
摘要 <p>In one implementation of the invention, a computer implemented method used in compiling a program includes identifying a covering load, which may be one of a set of covering loads, and a redundant load. The covering load and the redundant load have a first and second load type, respectively. The first and the second load type each may be one of a group of load types including a regular load and at least one speculative-type load. In one implementation, the group of load types includes at least one check-type load. One implementation of the invention is in a machine readable medium.</p>
申请公布号 EP1062576(A1) 申请公布日期 2000.12.27
申请号 EP19990909696 申请日期 1999.02.26
申请人 INTEL CORPORATION 发明人 WU, YOUFENG;LEE, YONG-FONG
分类号 G06F9/38;G06F9/45;(IPC1-7):G06F9/45 主分类号 G06F9/38
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