| 摘要 |
The method involves transmitting parallel data (DW) between a physical layer (PL) and a further layer (ATM-L) according to a standard layer model. A stand-by signal (RxClav) and an enabling or disabling signal (RxEnb) generated by the further layer are transmitted for controlling the data transmission. When the enabling or disabling signal or the stand-by signal change, a reaction occurs within at least one clock period (Fx). The enabling or disabling signal is indicated to the physical layer with a delay of a clock period. The parallel data which are transmitted to the clock controlled interface are controlled by the physical layer. A reload signal (dEnb&Clav) is generated by the delayed enabling or disabling signal and the stand-by signal using a logic element (AG) for time and clock correct control of the data to the interface. |
