发明名称 Multifunction floating point addition/subtraction pipeline
摘要 <p>An optimized multimedia execution unit (136) and method for performing vectored floating point and integer instructions. In one embodiment, the execution unit (136) includes an add/subtract pipeline (220) having far (230) and close (240) data paths. The far data path (230) is configured to handle effective addition operations, as well as effective subtraction operations for operands having an absolute exponent difference greater than one. The close data path (240), conversely, is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close data path (240) includes an adder unit (720) configured to generate a first (722A) and second (722B) output value. The first output value (722A) is equal to the first input operand plus an inverted version of the second input operand, while the second output value (722B) is equal to the first output value plus one. The two output values are conveyed to a multiplexer unit (740), which selects one of the output values as a preliminary subtraction result (742) based on a final selection signal (732) received from a selection unit (730). The selection unit (730) generates the final selection signal from a plurality of preliminary selection signals (752A-D) based on the carry in signal to the most significant bit of the first adder output value. Selection of the first or second output value in the close data path (240) effectuates the round-to-nearest operation for the output of the adder. The execution unit (136) may also be configured, in another embodiment, to perform floating point-to-integer and integer-to-floating point conversions. The floating point-to-integer conversions may be efficiently executed in the far data path (230) of the add/subtract pipeline (220), with the integer-to-floating point instructions executed in the close data path (240). The execution unit (136) may also include a plurality of add/subtract pipelines (220), allowing vectored add, subtract, and integer/floating point conversion instructions to be performed. The execution unit (136) may also be expanded to handle additional arithmetic instructions (such as reverse subtract and accumulate functions) by appropriate input multiplexing. Finally, functions like extreme value (minimum/maximum) and comparison instructions may also be implemented by proper multiplexing of output results. &lt;IMAGE&gt;</p>
申请公布号 EP1061436(A2) 申请公布日期 2000.12.20
申请号 EP20000203249 申请日期 1998.10.22
申请人 ADVANCED MICRO DEVICES INC. 发明人 OBERMAN, STUART F.;ROBERTS, MARK E.;JUFFA, NORBERT;WEBER, FREDERICK D.;CHERUKURI, RAVI KRISHNA;RAMANI, KRISHNAN
分类号 G06F7/57;G06F9/30;G06F9/302;G06F9/318;G06F9/38;H03M7/24;(IPC1-7):G06F7/50 主分类号 G06F7/57
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