| 摘要 |
Semiconductor testing equipment for the present invention includes a command pattern matching circuit 29, a timer circuit 17, an AND circuit 23 which ANDs acceptable product decision signal for inspecting decision change points for a device while being tested, and an OR circuit 24 for ORing the output signal of the timer 17 and the AND circuit 23. It also includes a pattern sequence control circuit 28 for changing the pattern sequence control operation upon receipt of the output signal of this OR circuit 24. The semiconductor testing equipment 1 monitors the changes in the outputs of the pins for all the devices under test 3, 3, . . . being simultaneously tested, detects acceptable products signals for the devices, when executing a specified mode processing of devices under test 3, 3, . . . , ends decision processing in the shortest time, and when the same decision process is repeated more than twice, invalidates the decision for the known defective devices under test 3, 3, . . . in the first processing, reduces the decision processing time and significantly reduces the testing time. |
