发明名称 Process for fabricating a semiconductor integrated circuit utilizing an exposure method
摘要 In a method of manufacturing a semiconductor device, a plurality of inter layer conductive path is formed through a first resist pattern which in turn is formed by an exposure of a hole pattern mask. A plurality of conductive lines is formed, adjacent to the layer of the conductive paths, through a second resist pattern which in turn is formed by double exposure of a line pattern mask and the hole pattern mask. Each conductive line is positioned on at least one of the conductive paths. Or alternatively, each conductive path is positioned between the lines.
申请公布号 US6162736(A) 申请公布日期 2000.12.19
申请号 US19970799595 申请日期 1997.02.12
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 NAKAO, SHUJI
分类号 G03F9/00;G03F7/00;G03F7/20;H01L21/027;H01L21/3205;H01L21/3213;(IPC1-7):H01L21/302 主分类号 G03F9/00
代理机构 代理人
主权项
地址