发明名称 Method for calibrating variable delay circuit and a variable delay circuit using the same
摘要 In a variable delay circuit calibrating method in which the state of connection of M delay stages connected in cascade through multiplexers and weighted differently is controlled by a control signal value to generate a calibrated amount of delay corresponding to a nominal amount of delay Ds which varies in a predetermined minimum nominal delay step ds, the method comprises the steps of: dividing an amount of delay Di measured for each given control signal value CCi by the minimum nominal delay step ds of a variable delay circuit; calculating first and second errors, Rk=Di-dsk and Rk+1=ds-Rk, between the value k of an integral part of the resulting quotient and two adjoining nominal amounts of delay Dsk and Dsk+1; making a check to determine if the first error Rk is smaller than an error held in a k-th row of a calibration table in correspondence with a nominal set signal value CS=k; if so, writing the first error Rk and the corresponding control signal value CCi over the existing values in the column of the k-th row of the calibration table; making a check to determine if the second error Rk+1 is smaller than an error held in a (k+1)-th row of the calibration table in correspondence with a nominal setting signal value CS=k+1; and, if so, writing the second error Rk+1 and the corresponding control signal value CCi over the existing values in the column of the (k+1)-th row of the calibration table. By repeatedly executing these steps for i=0 to i=2M-1, control signal values, which minimize errors between delay times of the variable delay circuit and the nominal amounts of delay, are generated in O-th to K-th rows of the calibration table in correspondence with the respective nominal setting signal values CS.
申请公布号 US6163759(A) 申请公布日期 2000.12.19
申请号 US19980193523 申请日期 1998.11.17
申请人 ADVANTEST CORPORATION 发明人 KITA, KAZUMI
分类号 G01R31/319;(IPC1-7):G01D18/00 主分类号 G01R31/319
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