| 摘要 |
PROBLEM TO BE SOLVED: To generate N pieces of sub-sampling clock signals having high timing accuracy to an edge of a main clock signal by connecting the 1st input, so as to receive a clock window signal and then connecting the 2nd input so as to receive the main clock signal. SOLUTION: First inputs of gate circuits 151-154 are connected to the different outputs of a clock window signal generator 149 respectively, and the 1st inputs of all circuits 151-154 receive N pieces of different clock window signals generated by the generator 149 respectively. Second inputs of the circuits 151-154 are connected together, so as to receive the main clock signals from a main clock signal input 29. The outputs of circuits 151-154 are connected to the clock signal inputs of track holding circuits 16-19. The sub-sampling clock signals generated by the circuits 151-154 are transmitted to the clock signal inputs of circuits 16-19. |
