Field effect transistor with improved source/drain diffusion regions having an extremely small capacitance

摘要

The invention provides a diffusion region structure in a semiconductor device wherein the diffusion region is applied with alternating voltages in an operation of the semiconductor device. The structure comprises at least one diffusion region being doped with an impurity of a first conductivity type at a first impurity concentration and also being provided in a semiconductor bulk region doped with an impurity of a second conductivity type at a second impurity concentration lower than the first impurity concentration, and at least a diffusion capacitance reduction layer provided under the diffusion region so as to be in contact with a bottom of the diffusion region. The diffusion capacitance reduction layer may be doped with an impurity of the second conductivity type at a third impurity concentration which is at least lower than the second impurity concentration of the semiconductor bulk region and not lower than zero or may be mode of an insulating material to thereby reduce a capacitance of the diffusion region.