发明名称 FREQUENCY PHASE LOCKED LOOP
摘要 PURPOSE: A frequency phase synchronous loop is provided to improve stability of operation by preventing offset and noise generated owing to detection of frequency aberration from having an effect on ultimate output. CONSTITUTION: A phase comparison unit(110) outputs phase aberration between phase of input data and phase of feedback signal. A frequency aberration detection unit(120) outputs frequency aberration between frequency of input data and frequency of feedback signal. An adder(130) outputs addition of the phase aberration and the frequency aberration. A loop filter(140) filters the output of the adder(130) into prescribed bandwidth. A voltage control oscillator(150) generates feedback signal which has a frequency and phase demanded by voltage level of the filtered signal. A synchronization detection unit(210) detects frequency aberration and generates switching control signal according to synchronization of input data and feedback signal. A switching unit(220) switches the adder(130) and the frequency aberration detection unit(120) according to the switching control signal.
申请公布号 KR100273965(B1) 申请公布日期 2000.12.15
申请号 KR19970080521 申请日期 1997.12.31
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 YOON, JEONG-SANG
分类号 H03L7/00;(IPC1-7):H03L7/00 主分类号 H03L7/00
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