| 摘要 |
PROBLEM TO BE SOLVED: To greatly improve the efficiency of redundancy relief by a simple circuit configuration. SOLUTION: Two redundancy bit regions bitL and bitR where a memory cell has been divided for each bit are provided at both the end parts of the bit region divided into N for a same bit, and a bit region with bit fail or the like is relieved by the redundancy bit regions bitR and bitL. For example, when bit regions bit1 and bit3 are defective, based on a relief signal, control logic and decode circuits connect I/O circuits DIO1 and DDIO0 to a bit region bit0 and the redundancy bit region bitL, respectively, outputs selection control signals SEL0 to SELn that shift I/O circuits DIO3 to DIOn to the redundancy bit region bitR from a bit region bit4 one by one for connecting, and the data I/O destination of the I/O circuits DIO0, DIO1, and DIO3 to DIOn is switched.
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