| 摘要 |
PROBLEM TO BE SOLVED: To provide a soft output Viterbi algorithm(SOVA) decoder that enables high-speed operation with a small circuit scale. SOLUTION: A path memory and likelihood update circuit 51 in a Two-Step SOVA decoder is provided with 4 RAMs 32x, 32y, 32z, 32w, that store path selection information denoting contents of a path with a higher likelihood in each state of a received convolution code. Path selection information by a plurality of times read and/or writes the RAMs 32x, 32y, 32z, 32w through a single address in the Two-Step SOVA decoder. Furthermore, in the Two-Step SOVA decoder, at least one piece of information from among a trace result signal denoting the result of tracing, a metric difference with respect to a maximum likelihood path, decoded data and logarithmic likelihood ratio information is read and/or written to/from the RAMs 32x, 32y, 32z, 32w, by using the path selection information and the address in common.
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