| 摘要 |
<p>The present invention extends a parallel DFE, by using look-ahead techniques in the selection stage to precompute the effect of previous blocks on each subsequent block, and thereby to remove the serial output dependency. The parallel DFE includes a multiplexor tree structure, that selects an appropriate output value for each block, and precomputes the effect of previous blocks on each subsequent block. A multiplexing delay algorithm, of order logN, is employed to resolve the output dependency, and thus speeds up parallel block processing DFEs. The disclosed DFE architecture can be combined with pipelining completely to eliminate the critical path problem. Pipelining reduces the required critical path timing to one multiplexing time. The disclosed multiplexor tree circuitry for the parallel decision-feedback equalizer (DFE) groups multiplexor blocks into groups of two, and provides at least one multiplexor for each block, i, to select an output value, yi, from among the possible precomputed values. The output of each parallel block depends on the possible precomputed values generated by the look-ahead processors for that block, as well as the actual values that are ultimately selected for each previous block. In order to reduce the delay in obtaining each actual output value, the present invention assumes that each block contains each possible value, and carries the assumption through to all subsequent blocks. Thus, the number of multiplexors required to select from among the possible values grows as N-logN, where N is the number of blocks. <IMAGE></p> |
