| 摘要 |
PROBLEM TO BE SOLVED: To provide such a logic circuit that the minimum pulse width of multiple frequency-divided clocks is maintained and a period needed for initialization to specific logic after a reset signal is activated does not depend upon the timing of activation of the reset signal. SOLUTION: This logic circuit inputs a clock signal 1 at the clock input terminal CL of a D flip-flop 4a and outputs a signal 3a from the output terminal Q. A signal 3a is supplied to the clock input terminal CL of a D flip-flop 4b and a signal 3b is outputted from the output terminal Q. The AND of the output of the output terminal QC of the D flip-flop 4a and the inverse of the reset signal 2a is supplied to the input terminal D of the D flip-flop 4a and the AND of the output of the output terminal QC of the D flip-flop 4b and the inverse of the reset signal 2b is supplied to the input terminal D of the D flip-flop 4b. The reset signals 2a and 2b are so set as to meet specific conditions. |
