| 摘要 |
PROBLEM TO BE SOLVED: To eliminate timing errors by changing the dimensions of a predetermined cell-forming element within a cell block where an input signal timing error has occurred for timing adjustment after an automatic layout step. SOLUTION: After a circuit design step 1, a temporary interconnection simulation step 2, and a layout design step 3 have been executed, timing detection is performed in an actual interconnection simulation step 4 based on the information gathered during the steps 1, 2, and 3. Then, if a timing error occurres in the following determination step 5, a gate layer of a cell suffering the timing error is selected in a timing adjustment step 7 to extract the length L of a transistor suitable for proper circuit signal timing. Thereafter, in a layout process 8, layout coordinates of a cell for which the L length is to be made variable in an EB processing 6 are extracted. After correcting the L length of the transistor in the process 6, layout data from which the timing error has been eliminated are extracted.
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