| 摘要 |
PROBLEM TO BE SOLVED: To insert a wait without causing command setting width to affect the output timing of a wait request. SOLUTION: While a cycle is started and a command is being outputted, a state transition circuit makes a command counter 12 count up. Command counter compare 13 compares the output of the command counter 12 with a command width set value and generates a command time-out output when they become equal to each other. The state transition circuit checks the level of the output of a synchronizing circuit 16 and makes the cycle wait in the same state when the level is '0'. When the level '1', state transition is caused and the wait counter 14 is made to count. The wait counter 14 when reaching IOCHRDY='0' returns to the last state, and the cycle is made to wait and extended until IOCHRDY='1'. While the wait counter 14 is counting, the wait counter compare 15 generates a wait time-out output when reaching a wait set value and the state transition circuit finishes the cycle.
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