| 摘要 |
PROBLEM TO BE SOLVED: To minimize the degradation of a main storage and to prevent the performance from deteriorating by reading and writing a cache memory as a substitute for access to a fault detected address by a processor. SOLUTION: A cache control part 119 receives an address of a defective memory 333 from a diagnostic device 4, writes a tag address constituting the high order part of the address of the defective memory 333 to a cache tag memory 113 accessed with a corresponding index, and sets '1' indicating error occurrence to the corresponding bit 114. The cache control part 119 receives a memory response inhibition signal 201 from a defective address detecting device 5, accesses a cache data memory 112, and writes or read the memory, thereby outputting the result to a system bus 9. A cache line whose error bit 114 is set to '1' is inhibited from being replaced and the cache data memory 112 is accessed to perform writing or reading.
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