| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce the size of a package and to simplify a packaging process. SOLUTION: The wafer level package is provided with a silicon chip 11 with an integrated circuit device 14, insulation layers 18a-18c for covering the integrated circuit device 14, a bonding pad 24 that is dispersively arranged along an edge 35 of the silicon chip 11 and further is electrically connected to the terminal of the integrated circuit device 14, a protection layer 30 for covering one portion of the insulation layer 18c and the bonding pad 24, a metal layer 34 that covers the exposed part of the bonding pad 24 and is extended to the edge 35, a packaging layer 36 that is provided on the protection layer 34, and a plurality of metal bumps 38 being provided on the metal layer 34.</p> |
