发明名称 SYSTEM FOR TESTING ARITHMETIC PROCESSOR IN MULTIPROCESSOR SYSTEM
摘要 PROBLEM TO BE SOLVED: To improve the test comprehensiveness of a random instruction combination test in a memory sharing type multiprocessor system. SOLUTION: An instruction assembling means 82 generates an instruction string by a random number, and embeds an instruction to perform write access and read access to the same physical address in the instruction string, and prepares write data 63 at the time of write access. An expected value generating means 83 generates the plural kinds of combination of expected values from write data 63-65 at the time of write access prepared by each processor in a processor group. An instruction string executing means 84 executes the prepared instruction string. An executed result comparing means 85 compares the executed result of the read access in the instruction string with the plural kind of combination of the expected value, and only when the instruction string executed result value of each processor is coincident with any of the plural kind of combination of the expected values, it is judged that the test result is successful.
申请公布号 JP2000322398(A) 申请公布日期 2000.11.24
申请号 JP19990129264 申请日期 1999.05.10
申请人 NEC SOFTWARE HOKURIKU LTD 发明人 HIROTA AKIHIKO
分类号 G06F15/177;G06F11/22 主分类号 G06F15/177
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