| 摘要 |
<p>PROBLEM TO BE SOLVED: To perform speedy frame synchronization by detecting whether an A2 frame pattern is received successively to an A1 frame, generating a frame pulse signal, detecting whether or not a frame synchronizing signal is detected successively as many times as specified and outputting a frame synchronism loss signal, and detecting whether or not this signal succeeds. SOLUTION: A byte arraying circuit 20 generates data by bytes from the output signal of a data width expanding circuit and an A1A1 pattern detecting circuit 119, an A2A2 pattern detecting circuit 129, and a successive pattern detecting circuit 150 performs A1A1 pattern detection. A byte array control circuit 110 having received a detection signal outputs the output signal of the byte arraying circuit 20. A frame synchronism loss detecting circuit 190 once detecting whether a frame synchronizing signal FRSYNC is not received successively four times generates a frame synchronism loss signal 00F and a frame synchronism error detecting circuit 180 detects whether or not this signal succeeds.</p> |
