MANUFACTURE OF SEMICONDUCTOR DEVICE AND MEMORY CELL

摘要

PROBLEM TO BE SOLVED: To obtain a method of manufacturing in which the source/drain region of an FET and a capacitor lower electrode are connected in small resistance without diffusion barrier in a memory cell provided with a stacked capacitor on a MOS field effect transistor (MOSFET). SOLUTION: A polysilicon plug 12 passing through a silicon oxide layer 14 on a silicon chip and connected in correspondence with a source/drain region of an FET is formed and a platinum layer is etched with a dielectric layer 16 as stopper to form a conductor 20. Then a high-dielectric layer 22, a capacitor upper electrode 24 and a dielectric layer 25 such as TEOS are layered, etching is carried out up to the polysilicon plug 12 leaving platinum conductors 20 to form an opening 32, a liner film 28 is formed, a conductive contact 30 is formed being insulated from the upper electrode 24, and the upper part is filled with TEOS 32 or the like.