发明名称 |
METHOD AND APPARATUS FOR JUMP DELAY SLOT CONTROL IN A PIPELINED PROCESSOR |
摘要 |
An improved method and apparatus for implementing instructions in a pipelined central processing unit (CPU) or user-customizable microprocessor. In a first aspect of the invention, an improved method of controlling branching and the execution of instructions within the pipeline is disclosed. In one embodiment, the method comprises defining three discrete delay slot modes within program jump instructions; these delay slot modes specify the execution of subsequent instructions or the stalling of the pipeline as desired by the programmer. In a second aspect of the invention, a method of synthesizing a processor design incorporating the aforementioned modes is disclosed. Exemplary gate logic synthesized using the aforementioned methods, and a computer system capable of implementing these methods, are also described.
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申请公布号 |
WO0070447(A2) |
申请公布日期 |
2000.11.23 |
申请号 |
WO2000US13233 |
申请日期 |
2000.05.12 |
申请人 |
ARC INTERNATIONAL U.S. HOLDINGS INC. |
发明人 |
WARNES, PETER;GRAHAM, CARL |
分类号 |
G06F9/38;G06F17/50;(IPC1-7):G06F9/00 |
主分类号 |
G06F9/38 |
代理机构 |
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地址 |
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