| 摘要 |
PURPOSE: A semiconductor memory device is provided which maximizes the efficiency by reducing the required test time and cost, by increasing the maximum number of dies which can be tested with a fixed system input/output channel. CONSTITUTION: A semiconductor memory device performs a high-speed test operation, being applied in a RAMBUS DRAM and a SYNC DRAM and DDR. The semiconductor memory device reduces the number of data input/output pads which are activated regarding as to the read operation during DA mode performing the repair as to the defective cell. The semiconductor memory device comprises: a first and a second data shift registers(14,16) shifting a first and a second data signal read from a memory cell according to the toggling of a control clock signal; a first and a second output drivers(24,26) which is driven under the control of the control clock signal and transferring each read data signal received from the first and the second data shift register to a first and a second output pad respectively; a first switching unit(30) which transfers the first read data to the first output pad, being turned on regardless of the entry to a mode(DA mode) which tests only a core cell and performs the repair operation as to a defective cell, being connected between the first output driver and the first output pad; and a second switching unit(32) which prevents the second read data from being transferred to the second output pad by being turned off when an activated DA mode entry judgement signal is applied, being connected between the second output driver and the second output pad.
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